DDR3/DDR2 Protocol Violation Software

Protocol and State Timing Analysis of DDR3/DDR2 Memory Buses

NEX-DDR-PROTOCOL New! Supports Tektronix' new TLA7BB4 modules.

A logic analyzer has the ability to acquire and save millions of cycles of DDR bus traffic with a single acquisition. Analysis of this information is difficult and time consuming. Identifying violations and their frequency and having a global picture of the activity on the bus is typically only done by customers that export the logic analyzer data and create software for custom analysis of the saved data. NEX-DDR-PROTOCOL, DDR3/DDR2 protocol violation software automates the analysis of your DDR bus to quickly and easily identify protocol violations, their frequency and also give a global view of the entire logic analyzer memory.

This software is available for most Nexus Technology DDR3 and DDR2 support software, adapters (interposers and NEXVu VDIMM's) and embedded supports.

Protocol Violations Reported

The following list of protocol violations can be reported by this software.

  1. Bank Violations Reported

    1. Active/Read/Write to Precharge in < tRASmin
    2. Active/Read/Write to Auto-Precharge (RDA/WRA) in < tRASmin
    3. Active/Read/Write to Precharge exceeded tRASmax
    4. Active to Auto-Precharge (RDA/WRA) exceeded tRASmax
    5. Active to read or write time in < tNARW
    6. Precharge to Activate or Precharge in < tRP
    7. Read burst interrupted by Activate/Read/Write
    8. Read to Precharge/Auto-Precharge in < tNRP
    9. Read to Write turn around time in < tNRTW
    10. Write burst interrupted by Activate/Read/Write
    11. Write to Precharge/Auto-Precharge in < tNWP
    12. Write to Read turn around time in < tNWR
    13. Write to Write time in < tCCD
    14. Read or Write to an inactive bank row
    15. Refresh command to an active bank
    16. Bank row X must be Precharged before being activated

  2. Rank Violations Reported

    1. Non-NOP/DES command to a refreshing rank in < tRFC
    2. Activate command on a refreshing rank

DDR Systems Supported

Protocol analysis is accomplished by modeling the DDR3/DDR2 SDRAM system in software. The NEX-DDR-PROTOCOL software sends the DDR commands stored on the logic analyzer and the timestamp associated with each command to this model. The model tracks the commands and reports any protocol errors based on these commands in time.

The NEX-DDR-PROTOCOL system is able to model DDR3/DDR2 systems with the following parameters.

  1. DDR3-1333, DDR3-1067, DDR3-800 specifications supported (On-The-Fly Burst option not supported)
  2. DDR2-800, DDR2-667, DDR2-533, DDR2-400 specifications supported
  3. 1-2 ranks (Chip Selects) (Future support will include 8)

  4. Standard DDR data addressing configurations (for row tracking and row/column address display

    1. DDR3: 32Mb-2Gb addressing over x4-x16 data buses
    2. DDR2: 16Mb-1Gb addressing over x4-x16 data buses
  5. Burst Lengths of 4 or 8 (On-The-Fly Burst option not supported)
  6. Additive Latencies of 0 to 10
  7. CAS Latencies of 2 to 11
  8. CAS Write Latencies of 5 to 8
  9. Completely variable specification timing parameter values

The NEX-DDR-PROTOCOL system is NOT able to model DDR3 systems using the following optional features.

  1. Partial Array Self-Refresh (PASR)
  2. Auto Self-Refresh (ASR)

Specification Timing Parameters Used

The following DDR3/DDR2 specification timing parameters are used during analysis.

  1. tCCD
  2. tRASmax
  3. tRASmin
  4. tRC
  5. tRCD
  6. tRP
  7. tRFC
  8. tRRD
  9. tRTP
  10. tWR
  11. tWTR

Ordering Information

Please send quote requests to quotes@nexustechnology.com. Purchase orders can be faxed to 877-595-8118.

All prices are US dollars only. We accept Visa, MasterCard, American Express and JCB. NET30 terms are available for established accounts.